1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to the structure within the memory cell array region of a static random access memory (referred to as SRAM hereinafter).
2. Description of the Prior Art
In general, a semiconductor memory device is constructed by memory cell array regions, a decoder circuit and a selection circuit that are placed adjacent to the memory cell array regions, and the like. Among these constituents the memory cell array regions in particular are constructed by regularly arranging the memory cells. Consequently, transistors (generally, MOS transistors) that constitute the memory cells are arranged regularly within the memory cell array regions.
However, in an SRAM there exist a power supply line Vcc and a grounding power supply line GND within a memory cell array region. Accordingly, the regularity of arrangement of the transistors that are in the portions where the power supply lines are arranged is disturbed.
The transistors constituting a memory cell are manufactured, within active regions formed during a selective oxidation. Most of these active regions are formed in a regular pattern within the memory cell array region, but, as mentioned above, the regularity of the formation pattern of the active regions that are adjacent to the power supply lines is disturbed.
The present inventor discovered that the nonuniformity of size in such areas relative to a design target value is very large compared with that in other active regions that are formed regularly. In particular, when the size of the active region is smaller than the design target value the gate width of the transistor formed within the active region becomes smaller than the design target value. That the gate width becomes small means that the drain current becomes correspondingly small, and the performance of the transistor is reduced.
A reduction in the transistor performance gives rise to a delay in the potential shift of the digit line connected to this transistor, causes the data output time to be delayed, and results in not only a marked reduction in the performance but also the generation of malfunctions of the semiconductor memory device.
Consequently, a semiconductor memory device that has a wiring region within the memory cell array region, has a problem in that the performance of a part of the transistors forming a memory cell is decreased, this leads to a reduction in the performance of the semiconductor memory device as a whole and a reduction in reliability due to generation of malfunctions.